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ADE7518
Table 59. Interrupt Priority SFR (IP, 0xB8)
Bit
7
6
5
4
3
2
1
0
Address
0xBF
0xBE
0xBD
0xBC
0xBB
0xBA
0xB9
0xB8
Mnemonic
PADE
Reserved
PT2
PS
PT1
PX1
PT0
PX0
Description
ADE Energy Measurement Interrupt Priority (1 = high, 0 = low).
This bit should be left cleared for proper operation.
Timer 2 Interrupt Priority (1 = high, 0 = low).
UART Serial Port Interrupt Priority (1 = high, 0 = low).
Timer 1 Interrupt Priority (1 = high, 0 = low).
INT1 (External Interrupt 1) Priority (1 = high, 0 = low).
Timer 0 Interrupt Priority (1 = high, 0 = low).
INT0 (External Interrupt 0) Priority (1 = high, 0 = low).
Table 60. Interrupt Enable and Priority 2 SFR (IEIP2, 0xA9)
Bit
7
6
5
4
3
2
1
0
Mnemonic
Reserved
PTI
Reserved
PSI
EADE
ETI
EPSM
ESI
Description
Reserved.
RTC Interrupt Priority (1 = high, 0 = low).
Reserved.
SPI/I 2 C Interrupt Priority (1 = high, 0 = low).
Enables the Energy Metering Interrupt (ADE). Set by the user.
Enables the RTC Interval Timer Interrupt. Set by the user.
Enables the PSM Power Supply Management Interrupt. Set by the user.
Enables the SPI/I 2 C Interrupt. Set by the user.
INTERRUPT PRIORITY
If two interrupts of the same priority level occur simultaneously, the polling sequence is observed (as shown in Table 61).
Table 61. Priority Within Interrupt Leve l
Source
IPSM
IRTC
IADE
WDT
IE0
TF0
IE1
TF1
ISPI/I2CI
RI/TI
TF2/EXF2
Priority
0 (Highest)
1
2
3
4
5
6
7
8
9
10 (Lowest)
Description
Power Supply Management Interrupt.
RTC Interval Timer Interrupt.
ADE Energy Measurement Interrupt.
Watchdog Timer Overflow Interrupt.
External Interrupt 0.
Timer/Counter 0 Interrupt.
External Interrupt 1.
Timer/Counter 1 Interrupt.
SPI/I 2 C Interrupt.
UART Serial Port Interrupt.
Timer/Counter 2 Interrupt.
Rev. 0 | Page 75 of 128
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